1. Field of Invention
The present invention relates to integrated circuits generally and more particularly to synthesis of radio-frequency integrated circuits.
2. Description of Related Art
The explosive growth of the communication markets and the demands for increasing connectivity and mobility have made RFIC (radio-frequency integrated circuit) designs ubiquitous in today's IC (integrated circuit) designs for applications ranging from mobile phones to laptop computers. The digital portion of the IC's can be designed with well-developed automation tools, while the analog and RF (radio frequency) portion is usually the bottle neck due to the lack of design automation. Over the last decade, there has been tremendous progress in the area of analog and RF design automation. (G. G. E. Gielen, R. A. Rutenbar, “Computer-Aided Design of Analog and Mixed-Signal Integrated Circuits”, Proc. IEEE, Vol. 88, No. 12, December 2000.) More specifically, point tools for particular design phases such as circuit synthesis, placement and routing have been developed. However, there are still many important design issues remaining unsolved because of the lack of systematic methodologies to address the entire design process. (M. Krasnicki, R. Phelps, R. A. Rutenbar, L. R. Carley, “MAELSTROM: Efficient Simulation-Based Synthesis for Analog Cells,” Proc. ACM/IEEE Design Automation Conference, June 1999.) (J. Cohn, D. Garrrod, R. A. Rutenbar, L. R. Carley, KOAN/ANAGRAMII: “New Tools for Device-Level Analog Layout”, IEEE J. Solid-State Cir., March 1991) (K. Lampaert, G. Gielen, W. M. Sansen, “A Performance-Driven Placement Tool for Analog Integrated Circuits”, IEEE J. Solid-State Circuits, Vol. 30, No. 7, July 1995.)
One such issue is parasitic closure, which refers to the requirement that a laid-out design must meet circuit performance specifications after taking the layout parasitics into account. The difficulty of parasitic closure is a direct result of the tight coupling between circuit sizing and layout, which is manifested in practically every RF circuit design. With conventional design methodologies, multiple iterations between front-end circuit sizing and back-end layout are normally required for RF designs to achieve parasitic closure. Since the newly developed RF circuit and layout synthesis point tools still treat circuit sizing and layout as separate tasks, the difficulty of parasitic closure remains a great challenge, especially for high-speed analog and radio-frequency circuits.
Conventionally, to account for layout effects, parasitics are extracted from an initial layout and included in the subsequent resizing. Such iterations are repeated until convergence is achieved. Since each circuit resizing only takes into account the parasitics of one layout, in particular the layout for the previous design cycle, convergence remains unpredictable. This calls for a more robust and efficient parasitic-aware circuit resizing approach. On the layout side, sensitivity based performance-driven layout techniques have been proposed to address electrical concerns. (K. Lampaert, G. Gielen, W. M. Sansen, “A Performance-Driven Placement Tool for Analog Integrated Circuits”, IEEE J. Solid-State Circuits, Vol. 30, No. 7, July 1995.) However such performance constraints usually over-constrain the layout without acknowledging that parasitic effects can often be compensated for by device resizing. In addition, linear sensitivity based performance models are too rudimentary to model performances with sufficient accuracy. Consequently, more accurate higher-order performance macromodels are necessary. Another issue with a conventional layout methodology is the separation of placement and routing. Interconnect parasitics cannot be estimated with sufficient accuracy during placement without routing details. Consequently, such an approach cannot achieve satisfactory placements when interconnect parasitics are critical to performance as in the case of RF circuits. Conventional approaches have combined placement and routing in substantially limited contexts. (M. Aktuna, R. A. Rutenbar, L. R. Carley, “Device-Level Early Floorplanning Algorithms for RF Circuits”, IEEE Trans. CAD, Vol. 18, No. 4, April, 1999.) (P. Vancorenland, G. Van der Plas, M. Steyaert, G. Gielen, W. Sanen, “A layout-aware synthesis methodology for RF circuits”, IEEE ICCAD, 2001.)
Thus, there is a need for improved synthesis for radio-frequency integrated circuits, including parasitic-aware circuit resizing, more accurate higher-order performance macromodels, performance-driven RF layout designs, and methods that integrate these aspects in an overall design process.